1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method and a semiconductor wafer. More particularly, the present invention relates to a semiconductor device manufacturing method which includes a process of forming a resist pattern on a silicon wafer using a resist mask, and a semiconductor wafer.
2. Description of the Related Art
Conventionally, when a semiconductor device is manufactured, devices such as transistors are formed on a semiconductor chip of a silicon wafer, and are connected using wiring lines formed on the semiconductor chip to realize a desired circuit. In this case, a high pattern density region and a low pattern density region are present in the pattern such as gate electrodes and wiring lines. For example, when bonding pads are formed in a peripheral section of the semiconductor chip, any circuitry is not arranged in the region where the bonding pads are formed and the neighborhood region. In this way, there is a low pattern density region in the peripheral section of the semiconductor chip. When there are a high pattern density area and a low pattern density area in patterns such as the gate electrodes and the wiring lines, the size of the gate electrode or wiring line becomes smaller or thinner than the size of the originally designed gate electrode or wiring line. As a result, the deviation is caused in the sizes of the gate electrodes and wiring lines. The reason is thought of as follows.
A photo-resist is used, when a fine pattern forming process such as a process of forming a gate electrode and a wiring line is carried out in a semiconductor device manufacturing process. A method of forming a positive type photo-resist pattern will be described below.
First, resist material is applied onto a silicon wafer and a resist layer is formed. Subsequently, the resist layer is exposed using a predetermined mask. The resist material in the exposed part is subjected to light reaction so that the resist material becomes soluble to resist developer. The soluble resist layer is developed using the resist developer. Then, only a part of the resist layer which has been not exposed remains and is formed as a resist pattern.
Generally, the resist pattern formed on the silicon wafer has a high pattern density region and a low pattern density region. In this case, in the development of the resist pattern, the development proceeds fast in the low pattern density region of the resist pattern, compared with the high pattern density region of the resist pattern. The difference in the development rate would be caused because development solution becomes excessive relatively in the low pattern density region of the resist pattern so that the development proceeds fast. As the result, the resist pattern is more excessively developed in the low pattern density region of the resist pattern than in the high pattern density region of the resist pattern. The gate electrode and the wiring line are formed using the above-mentioned resist pattern as a mask. For this reason, the deviation is caused in the size of the formed gate electrode and wiring line. The deviation in the size of the formed gate electrode leads the deviation in the characteristics of the gate electrode such as a threshold voltage. Also, the deviation in the size of the wiring line leads the deviation in the characteristics of the wiring line such as the wiring line capacity and the wiring line resistance. In any case, it brings about hindrance to the operation of the manufactured semiconductor circuit. In case of the worst, the wiring line is broken and a connection part of the wiring lines is broken. As a result, the formed device itself sometimes becomes fault.
Also, TEG (Test Element Group) chips for a test are formed on the silicon wafer other than product chips. Using the TEG chip, the analysis and evaluation of the process, device and circuit are carried out. The TEG chip has a TEG region which contains a TEG. The TEG is composed of a plurality of devices which are different from each other in size and a plurality of wiring patterns which are different from each other in width and length. The TEG is used to monitor the characteristics of the device formed on the silicon wafer and the forming state of the wiring lines.
A plurality of pads are provided for the TEG region of the TEG chip. Each device and each wiring line of the TEG are connected with the pads. By pushing probes of a test apparatus to the pads, the characteristics of each device and each wiring line of the TEG can be monitored. The size of the pad is larger than the device and the wiring line. Thus, the pad occupies a great part of the TEG region. Therefore, the TEG chip has a lower pattern density than the product chip. When the product chip is a chip for 64M DRAM, the pattern density of the product chip is 36.3% in the gate electrode and the pattern density of the TEG chip is 15.3%. In the future, even if the gate density of the product chip increases, it is difficult to increase the pattern density of the TEG chip. This is because the pattern density of the TEG region of the TEG chip is under a restriction in the total size of the plurality of pads which occupy a great part of the TEG region.
In this way, in case where devices and wiring lines are formed in the product chip and the TEG chip on the silicon wafer, the difference in pattern density is caused between the product chip and the TEG chip. Therefore, the deviation is caused in the sizes of the devices and wiring lines which are formed in the product chip and the TEG chip. Especially, the devices and the wiring lines of the TEG chip are formed in the lower pattern density than that of the product chip as mentioned above. Therefore, the device and the wiring line of the TEG chip are formed in the size different from the previously designed size. As a result, inconvenience is present that the characteristics of the device formed in the TEG chip cannot be correctly monitored using the device and the wiring lines formed actually. Especially, the above inconvenience is easy to occur in a gate electrode formed in the TEG chip.
Japanese Laid Open Patent Application (JP-A-Heisei 4-130709: a first conventional example) is known to prevent the occurrence of the deviation in the characteristics of the gate electrode and wiring line. In the first conventional example, a wiring pattern (a dummy pattern) is arranged in a free space in a semiconductor chip with no relation of circuit connection. FIG. 1 is a cross sectional view of a semiconductor memory device in the first conventional example. Referring to FIG. 1, there are a region where an actual pattern 102 is formed and a region where the actual pattern 102 is not formed on a semiconductor substrate 101. A dummy pattern 103 is formed in the region where the actual pattern 102 is not formed. Thus, the difference in pattern density on the semiconductor substrate 101 is made gentle. As a result, the deviation in the size of the wiring line formed on the semiconductor substrate 101 is prevented.
Otherwise, Japanese Laid Open Patent Application (JP-A-Heisei 9-311432: a second conventional example) is known to prevent the deviation in the characteristic of a gate electrode and a wiring line. In the second conventional example, a pattern is formed on the semiconductor chip using a photo-resist as a mask. In the method of forming a pattern, a dummy pattern is formed in a free space where an actual pattern is not formed, to have the same pattern width as the actual pattern. The pattern density of the free space where the dummy pattern is formed is approximately the same as that of a region where the actual pattern is formed.
FIG. 2 is a plan view showing the pattern which is formed by the pattern forming method for the semiconductor device in the second conventional example. Referring to FIG. 2, a product chip 111 and a TEG chip 112 are provided adjacently to each other. The product chip 111 contains a gate electrode 113. The TEG chip 112 contains a gate electrode 113, an impurity region 114 and a dummy pattern 116. The impurity region 114 is a part of the TEG. The product chip 111 and the TEG chip 112 are separated by a scribe region 115. The scribe region 115 is used when the chips are separated. The pattern width of the dummy pattern 116 is approximately equal to that of the gate electrode 113 formed in the product chip region. In this way, as shown in FIG. 2, in the second conventional example, the pattern density is made approximately uniform over the product chip 111 and the TEG chip 112. The second conventional example prevents the deviation in the size of the gate electrode and the size of the wiring line.
According to the second conventional example, the design of the dummy pattern is necessary in the TEG chip region in addition to the design of the TEG. Therefore, the design of the TEG chip region becomes complicated.